1. Field of the Invention
The present invention relates to a semiconductor device, and in particular to a semiconductor device which has an interconnection layer formed of a material containing Cu and Cu alloy and buried in a trench formed in an insulation layer.
2. Description of the Background Art
Recently, various considerations have also been taken for interconnection materials in response to the increasing demand for the high integration and rapid operation of semiconductor devices. In particular, the materials available for interconnection are believed to be extremely limited for generations after that with an interconnection width of approximately 0.15 .mu.m. Among such materials, it has recently been suggested that Cu is used as a material for interconnection.
FIG. 14 shows one example of the interconnection structure with Cu used as an interconnection material. The interconnection structure shown in FIG. 14 is formed by an interconnection process employing the so-called "Damascene method", which is described in, for example, "Interconnection Process Employing Damascene Method" published in monthly magazine Semiconductor World, December, 1995.
As shown in FIG. 14, a trench 2 is formed in an insulating layer 1 and a Cu interconnection layer 4 is formed in trench 2 with a base layer interposed therebetween. A cap layer 6 is formed to cover an upper surface of Cu interconnection layer 4. Cap layer 6 is formed of e.g. TiWN and acts to restrict oxidation of the upper surface of Cu interconnection layer 4. The provision of such a cap layer 6 can effectively restrict oxidation of the upper surface of Cu interconnection layer 4 and hence degradation in characteristics of Cu interconnection layer 4, such as increase in resistance of Cu interconnection layer 4.
The formation of such a cap layer 6 is described in, for example, "Damascene Cu interconnection capped by TiWN layer", Shingakugiho TECHNICAL REPORT OF IEICE. SDM96-169 (1996-12).
A method of fabricating the interconnection structure shown in FIG. 14 will now be described with reference to FIGS. 15-18 which are cross sections illustrating first to fourth steps of a process for fabricating the interconnection structure shown in FIG. 14, respectively.
Referring to FIG. 15, photolithography, etching and the like are employed to form trench 2 in insulating layer 1. Then, as shown in FIG. 16, chemical vapor deposition (CVD) or the like is employed to form a TiN layer 3a on which a Cu layer 4a is formed by sputtering or the like.
Then, chemical mechanical polishing (CMP) is applied to Cu layer 4a and TiN layer 3a to expose a surface of insulating layer 1 and also leave the Cu layer only in trench 2. Base layer 3 and Cu interconnection layer 4 are thus formed in trench 2, as shown in FIG. 17.
Sputtering or the like is then employed to form a TiWN layer 6a, as shown in FIG. 18. Then, the CMP is applied to TiWN layer 6a. The interconnection structure shown in FIG. 14 is obtained through this process.
While the formation of such a cap layer 6a can restrict oxidation of the upper surface of Cu interconnection layer 4, the Inventors of the present invention fabricated the interconnection structure shown in FIG. 14 as a trial and have found that exfoliation can be caused at the interface between cap layer 6 and Cu interconnection layer 4. One cause of the exfoliation is believed to be poor adhesion between Cu interconnection layer 4 and cap layer 6. The Inventors of the present invention have also found that the exfoliation is readily caused at the periphery of cap layer 6. Accordingly, it is believed that some stress is concentrated at the periphery of cap layer 6 and that stress concentration can be a cause of the exfoliation.
When such an exfoliation is caused at the interface between cap layer 6 and Cu interconnection layer 4, the upper surface of Cu interconnection layer 4 is oxidized and degradation in characteristic of Cu interconnection layer 4, such as increased resistance of Cu interconnection layer 4, is concerned. Such a degradation in characteristic of Cu interconnection layer 4 will lead to decreased yield and shortened lifetime of the interconnection.